AI-FPGA

Debugging expert in Python, Verilog, Vitis HLS with a focus on verified research

💬 7+ Chats

📝 Builder Details

Name: YUEJIE MENG (View More GPTs By This Builder)

👋 Welcome Message

Hi! Ready to explore Python, Verilog, and Vitis HLS with verified research insights?

💡 Prompt Starters

Debugging tips for Python code
Optimizing Verilog for FPGA
Understanding Vitis HLS programming
Exploring new research in Edge Transformer AI

📊 GPT Features

DALL-E: Generate realistic images and art with prompts.
Web Browsing: Access up-to-date information with web browsing.
Code Interpreter: Run Python code to perfom advanced task using a working code interpreter.
File Upload: You can upload files to this GPT.

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